1 ps8449a 10/09/00 features ? pi6c3q99x family provides following products: pi6c3q991: 32-pin plcc version PI6C3Q993: 28-pin qsop version ? inputs are 5v i/o tolerant ? 4 pairs of programmable skew outputs ? low skew: 200ps same pair; 250ps all outputs ? selectable positive or negative edge synchronization: excellent for dsp applications ? synchronous output enable ? output frequency: 3.75 mhz to 85 mhz ? 2x, 4x, 1/2, and 1/4 outputs ? 3 skew grades: ? 3-level inputs for skew and pll range control ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: < 200ps peak-to-peak ? industrial temperature range ? pin-to-pin compatible with idt qs5v991 and qs5v993 ? available in 32-pin plcc and 28-pin qsop description the pi6c3q99x family is a high fanout 3.3v pll-based clock driver intended for high performance computing and data-communica- tions applications. a key feature of the programmable skew is the ability of outputs to lead or lag the ref input signal. the pi6c3q991 has 8 programmable skew outputs in 4 banks of 2, while the PI6C3Q993 has 6 programmable skew outputs and 2 zero skew outputs. skew is controlled by 3-level input signals that may be hard- wired to appropriate high-mid-low levels. when the gnd/soe pin is held low, all the outputs are synchro- nously enabled. however, if gnd/soe is held high, all the outputs except 3q0 and 3q1 are synchronously disabled. furthermore, when the v ccq /pe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when v ccq /pe is held low, all the outputs are synchronized with the negative edge of ref. both devices have lvttl outputs with 12ma balanced drive outputs. pin configurations 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, PI6C3Q993 3.3v programmable skew pll clock driver superclock a ref v ccq fs 3f0 3f1 v ccq /pe v ccn 4q1 4q0 gnd 3q1 3q0 v ccn fb gnd test 2f1 2f0 gnd/soe 1f1 1f0 v ccn 1q0 1q1 gnd gnd 2q0 2q1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2f0 gnd/soe 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3f1 4f0 4f1 v ccq /pe v ccn 4q1 4q0 gnd gnd 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3q1 3q0 v ccn fb v ccn 2q1 2q0 3q0 fs v ccq ref gnd test 2f1 4 3 2 1 32 31 30 14 15 16 17 18 19 20 PI6C3Q993 pi6c3q991 28-pin q 32-pin j
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, pi6cq3993 3.3v programmable skew pll clock driver superclock a 2 ps8449a 10/09/00 pin descriptions e m a n n i pe p y tn o i t p i r c s e d l a n o i t c n u f f e rn it u p n i k c o l c e c n e r e f e r b fn it u p n i k c a b d e e f t s e t ) 1 ( n i s n o i t c e l e s w e k s . s t u p t u o l l a o t s e o g f e r . ) 1 e t o n f o s n o i t i d n o c r o f t p e c x e ( l l p s e l b a s i d , h g i h r o d i m n e h w . n o i t a r e p o l a m r o n r o f w o l t e s . t c e f f e n i n i a m e r ) 3 e l b a t e e s ( e o s / d n g ) 1 ( n i 0 q 3 - e t a t s w o l a n i ) 1 q 3 d n a 0 q 3 t p e c x e ( s t u p t u o k c o l c s p o t s t i , h g i h n e h w . e l b a n e t u p t u o s u o n o r h c n y s d n a l e v e l d i m t a d l e h s i t s e t n e h w . k c o l e s a h p n i a t n i a m o t l a n g i s k c a b d e e f e h t s a d e s u e b y a m 1 q 3 r o . l l = ] 0 : 1 [ f n n e h w s k n a b l a u d i v i d n i r o f s l o r t n o c e l b a s i d t u p t u o s a t c a s n i p ] 0 : 1 [ f n e h t , h g i h s i e o s / d n g . n o i t a r e p o l a m r o n r o f w o l e o s / d n g t e s v q c c e p /n i e h t h t i w d e z i n o r h c n y s e r a s t u p t u o e h t h g i h / w o l n e h w . l o r t n o c e g d e e v i t a g e n r o e v i t i s o p e l b a t c e l e s . k c o l c e c n e r e f e r e h t f o e g d e e v i t i s o p / e v i t a g e n ] 0 : 1 [ f nn i. e g n a r y c n e u q e r f r o s p a t w e k s 9 f o 1 g n i t c e l e s r o f s t u p n i l e v e l - 3 s fn i 2 e l b a t e e s . e g n a r y c n e u q e r f d e t a p i c i t n a n o d e s a b t i u c r i c r o t a l l i c s o e t a i r p o r p p a s t c e l e s ] 0 : 1 [ q nt u o . s t u p t u o w e k s o r e z d e x i f e r a 0 : 1 q 4 3 9 9 q 3 c 6 i p e h t n o . w e k s e l b a m m a r g o r p h t i w , s t u p t u o 2 f o s k n a b t u p t u o 4 v n c c r w ps r e f f u b t u p t u o r o f y l p p u s r e w o p v q c c r w py r t i u c r i c l a n r e t n i r e h t o d n a p o o l d e k c o l e s a h p r o f y l p p u s r e w o p d n gr w pd n u o r g note: 1. when test = mid and gnd/soe = high, pll remains active with nf[1:0] =ll functioning as an output disable control for individual output banks. skew selections (see table 3) remain in effect unless nf[1:0] = ll. logic block diagrams pi6c3q991 skew select 3 3 3 1f1:0 1q0 1q1 skew select 3 3 2f1:0 2q0 2q1 skew select 3 3 3f1:0 3q0 3q1 skew select 3 3 4f1:0 4q0 4q1 gnd/soe ref pll v ccq /pe fb fs PI6C3Q993 skew select 3 3 3 1f1:0 1q0 1q1 skew select 3 3 2f1:0 2q0 2q1 skew select 3 3 3f1:0 3q0 3q1 4q0 4q1 gnd/soe ref pll v ccq /pe fb fs
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, PI6C3Q993 3.3v programmable skew pll clock driver superclock a 3 ps8449a 10/09/00 programmable skew output skew with respect to the ref input is adjustable to compen- sate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. skew is selectable as a multiple of a time unit t u which is of the order of a nanosecond (see table 2). there are 9 skew configurations available for each output pair. these configu- rations are choosen by the nf1:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid-low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the skew selection table (table 3) shows how to select specific skew taps by using the nf1:0 control pins. external feedback by providing external feedback, the pi6c3q99x family gives users flexibility with regard to skew adjustment. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input fre- quency changes. w o l = s fd i m = s fh g i h = s fs t n e m m o c t ( n o i t a l u c l a c t i n u g n i m i t u )f x 4 4 ( / 1 m o n )f x 6 2 ( / 1 m o n )f x 6 1 ( / 1 m o n ) f ( e g n a r y c n e u q e r f o c v m o n ) ) 2 , 1 ( z h m 5 3 o t 5 1z h m 0 6 o t 5 2z h m 5 8 o t 0 4 e g n a r t n e m t s u j d a w e k s ) 3 ( . x a m t n e m t s u j d a s n 9 0 . 9 9 4 % 4 1 s n 3 2 . 9 3 8 % 3 2 s n 8 3 . 9 5 3 1 % 7 3 s e e r g e d e s a h p s n e m i t e l c y c f o % f , 1 e l p m a x e m o n z h m 5 1 =t u s n 2 5 . 1 = f , 2 e l p m a x e m o n z h m 5 2 =t u s n 1 9 . 0 =t u s n 4 5 . 1 = f , 3 e l p m a x e m o n z h m 0 3 =t u s n 6 7 . 0 =t u s n 8 2 . 1 = f , 4 e l p m a x e m o n z h m 0 4 =t u s n 6 9 . 0 =t u s n 6 5 . 1 = f , 5 e l p m a x e m o n z h m 0 5 =t u s n 7 7 . 0 =t u s n 5 2 . 1 = f , 6 e l p m a x e m o n z h m 0 8 =t u s n 8 7 . 0 = table 2. pll programmable skew range and resolution table notes: 1. the device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. selecting the appropriate fs value based on input frequency range allows the pll to operate in its ?sweet spot? where jitter is lowest. 2. the level to be set on fs is determined by the nominal operating frequency of the vco and time unit generator. the vco frequency always appears at 1q1:0, 2q1:0, and the higher outputs when they are operated in their undivided modes. the frequency appearing at the ref and fb inputs will be the same as the vco when the output connected to fb is undivided. the frequency of the ref and fb inputs will be 1/2 or 1/4 the vco frequency when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed q output is used for feedback, then adjustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed ?4t u in addition to whatever skew value is programmed for those outputs. ?max adjustment? range applies to output pairs 3 and 4 where 6 t u skew adjustment is possible and at the lowest f nom value.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, pi6cq3993 3.3v programmable skew pll clock driver superclock a 4 ps8449a 10/09/00 0 : 1 f n) 2 # , 1 # r i a p ( w e k s) 3 # r i a p ( w e k s) 4 # r i a p ( w e k s ) 1 ( l l ) 2 ( t 4 ? u 2 y b e d i v i d2 y b e d i v i d m lt 3 ? u t 6 ? u t 6 ? u h lt 2 ? u t 4 ? u t 4 ? u l mt 1 ? u t 2 ? u t 2 ? u m mw e k s o r e zw e k s o r e zw e k s o r e z h mt 1 + u t 2 + u t 2 + u l ht 2 + u t 4 + u t 4 + u m ht 3 + u t 6 + u t 6 + u h ht 4 + u 4 y b e d i v i dd e t r e v n i ) 3 ( table 3. skew selection table for output pairs notes: 1. programmable skew on pair #4 is not applicable for the pi6c993. 2. ll disables outputs if test = mid and gnd/ soe = high. 3. when pair #4 is set to hh (inverted), gnd/soe disables pair #4 high when v ccq /pe = high, gnd/soe disables pair #4 low when v ccq / pe = low supply voltage to ground ........................................................ ?0.5v to 7.0v dc input voltage v i .................................................................... ?0.5v to v cc + 0.5v maximum power dissipation at t a = 85c, plcc ......................... 0.80 watts qsop ....................... 0.66 watts tstg storage temperature .................................................... ?65c to 150c table 4. absolute maximum ratings table 5. recommended operating range l o b m y sn o i t p i r c s e d x 9 9 q 3 c 6 i p 5 - x 9 9 q 3 c 6 i p ) l a i r t s u d n i ( 2 - x 9 9 3 c 6 i p ) l a i c r e m m o c ( s t i n u . n i m. x a m. n i m. x a m v c c y l p p u s r e w o p e g a t l o v 0 . 36 . 30 . 36 . 3v t a g n i t a r e p o t n e i b m a e r u t a r e p m e t 0 4 ?5 800 7c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, PI6C3Q993 3.3v programmable skew pll clock driver superclock a 5 ps8449a 10/09/00 l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. x a ms t i n u v h i e g a t l o v h g i h t u p n i h g i h c i g o l d e e t n a r a u g ) y l n o s t u p n i b f , f e r ( 0 . 2 v v l i e g a t l o v w o l t u p n i w o l c i g o l d e e t n a r a u g ) y l n o s t u p n i b f , f e r ( 8 . 0 v h h i e g a t l o v h g i h t u p n i ) 1 ( y l n o s t u p n i l e v e l - 3v c c 6 . 0 ? v m m i e g a t l o v d i m t u p n i ) 1 ( y l n o s t u p n i l e v e l - 3v c c 2 /3 . 0 ?v c c 3 . 0 + 2 / v l l i e g a t l o v w o l t u p n i ) 1 ( y l n o s t u p n i l e v e l - 36 . 0 ? i n i ? , f e r ( t n e r r u c e g a k a e l t u p n i ) y l n o s t u p n i b f v n i v = c c , d n g r o v c c . x a m = 5 a ? i 3 ? t n e r r u c c d t u p n i l e v e l - 3 ) 0 : 1 f n , s f , t s e t ( v n i v = c c v n i v = c c 2 / v n i d n g = l e v e l h g i h l e v e l d i m l e v e l w o l 0 0 2 0 5 0 0 2 ? i u p ? t n e r r u c p u - l l u p t u p n i v ( q c c ) e p / v c c v , . x a m = n i d n g =0 0 1 ? i d p ? t n e r r u c n w o d - l l u p t u p n i ) e o s / d n g ( v c c v , . x a m = n i v = c c 0 0 1 v h o e g a t l o v h g i h t u p t u ov c c i , . n i m = h o= a m 2 1 ?2 . 2 v v l o e g a t l o v w o l t u p t u ov c c i , . n i m = l o= a m 2 15 5 . 0 table 6. dc characteristics over operating range note: 1. these inputs are normally wired to v cc , gnd, or unconnected. internal termination resistors bias unconnected inputs to v cc /2. if these inputs are switched, the function and timing of the outputs may glitched, and the pll may require an additional t lock time before all datasheet limits are achieved. l o b m y sr e t e m a r a pn o i t i d n o c t s e t. p y t. x a ms t i n u i q c c t n e r r u c y l p p u s r e w o p t n e c s e i u q v c c , w o l = f e r , . d i m = t s e t , . x a m = d e d a o l n u s t u p t u o l l a , w o l = e o s / d n g 0 . 85 1a m d i c c h g i h t u p n i r e p t n e r r u c y l p p u s r e w o p ) 1 ( v c c v , . x a m = n i v 0 . 3 =0 . 10 3a i d c c t u p t u o r e p t n e r r u c y l p p u s r e w o p c i m a n y d ) 1 ( v c c c , . x a m = l f p 0 =5 50 9z h m / a i c t n e r r u c y l p p u s r e w o p l a t o t ) 1 ( v c c f , v 3 . 3 = f e r c , z h m 0 2 = l f p 0 6 1 = ) 2 ( 9 2 a m i c t n e r r u c y l p p u s r e w o p l a t o t ) 1 ( v c c f , v 3 . 3 = f e r c , z h m 3 3 = l f p 0 6 1 = ) 2 ( 2 4 i c t n e r r u c y l p p u s r e w o p l a t o t ) 1 ( v c c f , v 3 . 3 = f e r c , z h m 6 6 = l f p 0 6 1 = ) 2 ( 6 7 table 7. power supply characteristics notes: 1. guaranteed by characterization but not production tested. 2. for 8 outputs each loaded with 20pf.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, pi6cq3993 3.3v programmable skew pll clock driver superclock a 6 ps8449a 10/09/00 output v cc 150 w 150 w 20pf 1ns 1ns 3.0v 2.0v vth=1.5v 0.8v 0v lvttl input test waveform t orise t pwh t pwl t ofall 2.0v 0.8v lvttl output waveform p o s qc c l p s t i n u . p y t. x a m. p y t. x a m c n i 46 5 7 f p table 8. capacitance (t a = 25c, f = 1 mhz, v in = 0v) ac test loads and waveforms
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, PI6C3Q993 3.3v programmable skew pll clock driver superclock a 7 ps8449a 10/09/00 n o i t p i r c s e d 2 - 1 9 9 q 3 c 6 i p 2 - 3 9 9 q 3 c 6 i p 5 - 1 9 9 q 3 c 6 i p 5 - 3 9 9 q 3 c 6 i p 1 9 9 q 3 c 6 i p 3 9 9 q 3 c 6 i p s t i n u l o b m y s. n i m. p y t. x a m. n i m. p y t. x a m. n i m. p y t. x a m f m o n e g n a r y c n e u q e r f o c v2 e l b a t e e s2 e l b a t e e s2 e l b a t e e s t h w p r h g i h h t d i w e s l u p f e r ) 1 1 ( 0 . 30 . 30 . 3 s n t l w p r w o l h t d i w e s l u p f e r ) 1 1 ( 0 . 30 . 30 . 3 t u t i n u e m i t w e k s e l b a m m a r g o r p3 e l b a t e e s3 e l b a t e e s3 e l b a t e e s t r p w e k s ) 1 q x , 0 q x ( w e k s r i a p - d e h c t a m t u p t u o o r e z ) 3 , 2 , 1 ( 5 0 . 00 2 . 01 . 05 2 . 01 . 05 2 . 0 s n t 0 w e k s c ) s t u p t u o l l a ( w e k s t u p t u o o r e z l f p 0 = ) 4 , 1 ( 1 . 05 2 . 05 2 . 05 . 03 . 05 7 . 0 t 1 w e k s ) s t u p t u o s s a l c e m a s , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 5 , 1 ( 5 2 . 00 5 . 06 . 07 . 06 . 00 . 1 t 2 w e k s ) d e d i v i d - d e d i v i d , d e t r e v n i - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 5 , 1 ( 0 3 . 02 . 15 . 02 . 10 . 15 . 1 t 3 w e k s ) s t u p t u o s s a l c t n e r e f f i d , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 5 , 1 ( 5 2 . 00 5 . 05 . 07 . 07 . 02 . 1 t 4 w e k s ) d e t r e v n i - d e d i v i d , d e d i v i d - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 5 , 1 ( 0 5 . 00 9 . 05 . 00 . 12 . 17 . 1 t v e d w e k s e c i v e d - o t - e c i v e d ) 6 , 2 , 1 ( 5 7 . 05 2 . 15 6 . 1 t d p y a l e d n o i t a g a p o r p b f o t t u p n i f e r ) 8 , 1 ( 5 2 . 0 ?05 2 . 05 . 0 ?05 . 07 . 0 ?07 . 0 t v c d o % 0 5 m o r f n o i t a r a v e l c y c y t u d t u p t u o ) 1 ( 2 . 1 ?02 . 12 . 1 ?02 . 12 . 1 ?02 . 1 t h w p % 0 5 m o r f n o i t a i v e d e m i t h g i h t u p t u o ) 9 , 1 ( 0 . 25 . 20 . 3 t l w p % 0 5 m o r f n o i t a i v e d e m i t w o l t u p t u o ) 0 1 , 1 ( 5 . 20 . 35 . 3 t e s i r o e m i t e s i r t u p t u o ) 1 ( 5 1 . 00 . 18 . 15 1 . 00 . 18 . 15 1 . 05 . 15 . 2 t l l a f o e m i t l l a f t u p t u o ) 1 ( 5 1 . 00 . 18 . 15 1 . 00 . 18 . 15 1 . 05 . 15 . 2 t k c o l e m i t k c o l l l p ) 7 , 1 ( 5 . 05 . 05 . 0s m t r j r e t t i j t u p t u o e l c y c - o t - e l c y c ) 1 ( s m r5 20 40 4 s p k a e p - o t - k a e p0 0 20 0 20 0 2 table 9. switching characteristics over operating range notes: 1. all timing tolerances apply for f nom 3 25mhz. guaranteed by design and characterization, not subject to 100% production testing. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 4. t skew0 is the skew between outputs when they are selected for 0t u . 5. there are 3 classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 6. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) 7. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 8. t pd is measured with ref input rise and fall times (from 0.8v to 2.0v) of 1.0ns. 9. measured at 2.0v. 10. measured at 0.8v. 11. refer to table12 for more detail.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, pi6cq3993 3.3v programmable skew pll clock driver superclock a 8 ps8449a 10/09/00 t ref t rpwh t odcv t skewpr t skew0, 1 t skew3,4 t skew3,4 t skew3,4 t skew2,4 t skew1,3,4 t skewpr t skew0, 1 t pd t odcv t rpwl t jr ref fb q other q inverted q ref divided by 2 ref divided by 4 t skew2 t skew2 l o b m y sn o i t p i r c s e d. n i m. x a ms t i n u t r t , f v 0 . 2 o t v 8 . 0 , s e m i t l l a f d n a e s i r t u p n i m u m i x a m0 1v / s n t c w p w o l r o h g i h , e s l u p k c o l c t u p n i3s n d h e l c y c y t u d t u p n i0 10 9% table 12. input timing requirements notes: 1. input timing requirements are guaranteed by design but not tested. where pulse width implied by d h is less than t pwc limit, t pwc limit applies. ac timing diagram notes: v ccq /pe: the ac timing diagram above applies to v ccq /pe=v cc . for v ccq /pe=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align . skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 20pf and terminated with 75ohm to v cc /2. t skewpr : the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . t skew0 : the skew between outputs when they are selected for 0t u. t dev : the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. t lock : the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. t pwh is measured at 2.0v. t pwl is measured at 0.8v. t orise and t ofall are measured between 0.8v and 2.0v.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, PI6C3Q993 3.3v programmable skew pll clock driver superclock a 9 ps8449a 10/09/00 32-pin plcc package diagram .386 .394 .053 .069 .004 .010 seating plane .025 bsc .007 .010 .228 .244 0.150 0.157 1 28 .016 .050 x.xx x.xx denotes dimensions in millimeters 0.635 9.804 10.009 1.35 1.75 5.79 6.19 0.41 1.27 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 .033 0.84 .015 x 45? ref 28-pin qsop package diagram
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3q991, pi6cq3993 3.3v programmable skew pll clock driver superclock a 10 ps8449a 10/09/00 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com e d o c g n i r e d r oe d o c e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o j 1 9 9 q 3 c 6 i p2 3 jc c l p n i p - 2 3 l a i c r e m m o c j 2 - 1 9 9 q 3 c 6 i p2 3 jc c l p n i p - 2 3 j 5 - 1 9 9 q 3 c 6 i p2 3 jc c l p n i p - 2 3 j i - 1 9 9 q 3 c 6 i p2 3 jc c l p n i p - 2 3 l a i r t s u d n i j i 5 - 1 9 9 q 3 c 6 i p2 3 jc c l p n i p - 2 3 q 3 9 9 q 3 c 6 i p8 2 qp o s q n i p - 8 2 l a i c r e m m o c q 2 - 3 9 9 q 3 c 6 i p8 2 qp o s q n i p - 8 2 q 5 - 3 9 9 q 3 c 6 i p8 2 qp o s q n i p - 8 2 q i - 3 9 9 q 3 c 6 i p8 2 qp o s q n i p - 8 2 l a i r t s u d n i q i 5 - 3 9 9 q 3 c 6 i p8 2 qp o s q n i p - 8 2 ordering information
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